The present invention relates to a method for designing a semiconductor integrated circuit with parasitic elements extracted from layout data to analyze the operation timing of circuit elements.
As the design rule for a semiconductor integrated circuit fabrication process has been reduced year after year, it has become increasingly important to analyze the operation timing of circuit elements, included in the circuit being designed, even more accurately by extracting various parasitic elements therefrom. This is because the operation speed of the circuit will be affected even more seriously by those parasitic elements like wire resistance and capacitance components. Thus, in the timing simulation, it should be estimated as accurately as possible how much delay will be caused by the parasitic elements that are unavoidably added to every interconnection line.
In a known semiconductor integrated circuit design process, the parasitic elements should be extracted one by one from given layout data for all graphics patterns. That is to say, the wire resistance and capacitance components should be estimated for every single graphics pattern.
According to such a one-by-one extraction technique, however, it takes an enormous amount of time to process a huge number of graphics patterns for a large-scale integrated circuit. Thus, the required processing time will increase almost exponentially as the integrated circuit to be designed is scaled up.
It is therefore an object of the present invention to extract those parasitic elements in a much shorter time for improving the efficiency of the timing simulation.
The present inventors found that some of the paths, interconnecting multiple elements together in a circuit being designed, do not have to be extracted as paths with parasitic elements, because the timing constraints imposed on those paths are not so tight. Thus, to achieve the above object, we extract no paths other than those indispensable for the timing simulation with that finding in mind.
Specifically, a first inventive method is adapted to design a semiconductor integrated circuit, including multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements. The method includes the steps of: a) sorting out at least one of the paths, which is expected to cause a delay exceeding a predetermined amount of time, as a target path according to a netlist describing topology information about interconnections among the circuit elements; b) forming graphics patterns -for the respective circuit elements and laying out the graphics patterns according to the netlist, thereby generating layout data; and c) extracting the parasitic elements from at least one of the graphics patterns, which correspond to the target path, in accordance with the layout data.
According to the first method, at least one of the paths, which is expected to cause a delay exceeding a predetermined amount of time, is sorted out as a target path according to a netlist describing topology information about interconnections among the circuit elements. Then, parasitic elements are extracted from at least one of the graphics patterns, corresponding to the target path, in accordance with the layout data generated from the netlist. That is to say, according to the present invention, there is no need to extract the parasitic elements from all the paths anymore. As a result, the parasitic elements can be extracted much more efficiently and rapidly, thus meeting the demand for accurate and quick simulation on the operation timing of the circuit elements.
A second inventive method is also adapted to design a semiconductor integrated circuit, including multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements. The method includes the steps of: a) forming graphics patterns for the respective circuit elements and laying out the graphics patterns according to a netlist describing topology information about interconnections among the circuit elements, thereby generating layout data including information about wire lengths; b) estimating wire lengths of interconnection lines included in each of the paths in accordance with the layout data and sorting out at least one of the paths, in which at least one of the wire lengths estimated exceeds a predetermined length, as a target path; and c) extracting the parasitic elements from at least one of the graphics patterns, which correspond to the target path, in accordance with the layout data.
According to the second method, the wire lengths of interconnection lines included in each of the paths are estimated in accordance with the layout data obtained from the netlist. Next, at least one of the paths, in which at least one of the wire lengths estimated exceeds a predetermined length, is sorted out as a target path. Then, parasitic elements are extracted from at least one of the graphics patterns, corresponding to the target path, in accordance with the layout data. Thus, according to the present invention, there is no need to extract the parasitic elements from all the paths anymore. As a result, the parasitic elements can be extracted much more efficiently and rapidly, thus meeting the demand for accurate and quick simulation on the operation timing of the circuit elements.
A third inventive method is also adapted to design a semiconductor integrated circuit, including multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements. The method includes the steps of: a) forming graphics patterns for the respective circuit elements and laying out the graphics patterns according to a netlist describing topology information about interconnections among the circuit elements, thereby generating layout data including information about wire lengths; b) estimating the length of at least one pair of interconnection lines, which are included in two adjacent ones of the paths and are substantially parallel to each other, in accordance with the layout data and sorting out at least two of the paths, in which the estimated length of the parallel interconnection lines exceeds a predetermined length, as target paths; and c) extracting the parasitic elements from at least one of the graphics patterns, which correspond to the target paths, in accordance with the layout data.
According to the third method, the length of at least one pair of interconnection lines, which are included in two adjacent ones of the paths and are substantially parallel to each other, is estimated in accordance with the layout data obtained from the netlist. Next, at least two of the paths, in which the estimated length of the parallel interconnection lines exceeds a predetermined length, are sorted out as target paths. Then, parasitic elements are extracted from at least one of the graphics patterns, corresponding to the target paths, in accordance with the layout data. Thus, according to the present invention, there is no need to extract the parasitic elements from all the paths anymore. As a result, the parasitic elements can be extracted much more efficiently and rapidly, thus meeting the demand for accurate and quick simulation on the operation timing of the circuit elements.
In one embodiment of the second or third method of the present invention, the step b) preferably includes the step of sorting out at least one of the paths, which is expected to cause a delay-exceeding a predetermined amount of time, as the target path in accordance with the layout data. Generally speaking, a path might cause a delay exceeding a predetermined amount of time even though the total wire length of interconnection lines, included in the path, is less than the predetermined length. According to this embodiment, however, such a path can also be sorted out, thus improving the accuracy of the timing simulation.
A fourth inventive method is also adapted to design a semiconductor integrated circuit, including multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements. The method includes the steps of: a) estimating delays, which will be caused by the respective paths, according to a netlist describing topology information about interconnections among the circuit elements; b) forming graphics patterns for the respective circuit elements and laying out the graphics patterns according to the netlist, thereby generating layout data; c) sorting out at least one of the paths, of which the estimated delay exceeds a predetermined amount of time, as a target path; or cxe2x80x2) estimating wire lengths of interconnection lines included in each of the paths in accordance with the layout data and sorting out at least one of the paths, in which at least one of the wire lengths estimated exceeds a predetermined length, as the target path; and d) extracting the parasitic elements from at least one of the graphics patterns, which correspond to the target path, in accordance with the layout data.
According to the fourth method, at least one of the paths, of which the estimated delay exceeds a predetermined amount of time, is sorted out as the target path. Or the wire length of interconnection lines, included in each of the paths, are estimated in accordance with the layout data and at least one of the paths, in which at least one of the wire lengths estimated exceeds a predetermined length, is sorted out as the target path. Then, parasitic elements are extracted from at least one of the graphics patterns, corresponding to the target path, in accordance with the layout data. Thus, according to the present invention, there is no need to extract the parasitic elements from all the paths anymore. As a result, the parasitic elements can be extracted much more efficiently and rapidly, thus meeting the demand for accurate and quick simulation on the operation timing of the circuit elements.
A fifth inventive method is also adapted to design a semiconductor integrated circuit, including multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements. The method includes the steps of: a) estimating delays, which will be caused by the respective paths, according to a netlist describing topology information about interconnections among the circuit elements; b) forming graphics patterns for the respective circuit elements and laying out the graphics patterns according to the netlist, thereby generating layout data; c) sorting out at least one of the paths, of which the estimated delay exceeds a predetermined amount of time, as a target path; or cxe2x80x2) estimating the length of at least one pair of interconnection lines, which are included in two adjacent ones of the paths and are substantially parallel to each other, in accordance with the layout data and sorting out at least two of the paths, in which the estimated length of the parallel interconnection lines exceeds a predetermined length, as the target paths; and d) extracting the parasitic elements from at least one of the graphics patterns, which correspond to the target path, in accordance with the layout data.
According to the fifth method, at least one of the paths, of which the estimated delay exceeds a predetermined amount of time, is sorted out as a target path. Or the length of at least one pair of interconnection lines, which are included in two adjacent ones of the paths and are substantially parallel to each other, is estimated in accordance with the layout data and at least two of the paths, in which the estimated length of the parallel interconnection lines exceeds a predetermined length, are sorted out as the target paths. Then, parasitic elements are extracted from at least one of the graphics patterns, corresponding to the target paths, in accordance with the layout data. Thus, according to the present invention, there is no need to extract the parasitic elements from all the paths anymore. As a result, the parasitic elements can be extracted much more efficiently and rapidly, thus meeting the demand for accurate and quick simulation on the operation timing of the circuit elements.
In one embodiment of the present invention, the step cxe2x80x2) preferably includes the step of sorting out the least two paths, in which the estimated length of the parallel interconnection lines exceeds the predetermined length, as paths to be analyzed for crosstalk. And the step d) preferably includes the step of extracting the parasitic elements from the graphics patterns corresponding to the paths to be analyzed for crosstalk. In such an embodiment, not only the paths that will cause delays exceeding the predetermined amount of time, but also paths that will cause crosstalk noise between adjacent interconnection lines can be extracted. As a result, the simulated operation timing of the integrated circuit can be even closer to the actual operation timing of the circuit.